This invention relates to an externally testable LSI device incorporating circuits for testing, such as latch/shift registers, and a method of testing the LSI chip. Particularly, the invention relates to an LSI chip incorporating functional blocks such as RAM, ROM and peripheral logic circuits capable of being tested externally, and a method of testing the functional blocks of LSI through the test pattern generation.
Conventional LSI devices incorporating memory blocks such as RAM and ROM together with random logic circuits have their contents of memory blocks varied depending on the states of flip-flops in the periphery of the memory blocks. Therefore, it is difficult to make access to the memory blocks from the LSI edge node (bonding pads) for setting or reading out their contents. On this account, in diagnosing an LSI chip incorporating memory blocks, a test pattern is prepared exclusive of the memory block and uncertainty value "X" is inserted in the output signals of the memory blocks. A diagnostic technique of this kind is disclosed in JP-A-No. 62-34244 (published on Feb. 14, 1987) by the same inventors of the present invention.
The above-mentioned conventional technique, in which uncertainty value "X" is inserted in the output signals of memory blocks in conducting a diagnosis, makes it infeasible to detect defects in the peripheral logic circuits which are the signal propagation path for the memory blocks, resulting in a lower defect detection rate for the whole LSI chip inclusive of the memory block peripheral logic circuits.
The same problem arises in testing comprehensive LSI chips in which various functional blocks are included. Namely, it is difficult to test a specific block such as a memory block independently of other blocks in mutual connection.